參數(shù)資料
型號： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強塑料PC卡控制器數(shù)據(jù)手冊
文件頁數(shù)： 61/125頁
文件大?。?/td> 716K
代理商： PCI1520-EP
4
–
8
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-to-PCI bridge secondary status register and indicates
CardBus-related device information to the host system. This register is very similar to the status register (offset 06h,
see Section 4.5); status bits are cleared by writing a 1. See Table 4
–
5 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Secondary status
Type
RC
RC
RC
RC
RC
R
R
RC
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Secondary status
16h
Read-only, Read/Clear
0200h
Table 4
–
5. Secondary Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
CBPARITY
RC
Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data).
14
CBSERR
RC
Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1520 does not
assert CSERR.
13
CBMABORT
RC
Received master abort. Bit 13 is set when a cycle initiated by the PCI1520 on the CardBus bus has been
terminated by a master abort.
12
REC_CBTA
RC
Received target abort. Bit 12 is set when a cycle initiated by the PCI1520 on the CardBus bus is terminated
by a target abort.
11
SIG_CBTA
RC
Signaled target abort. Bit 11 is set by the PCI1520 when it terminates a transaction on the CardBus bus
with a target abort.
10
–
9
CB_SPEED
R
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the
PCI1520 asserts CB_SPEED at a medium speed.
8
CB_DPAR
RC
CardBus data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
b. The PCI1520 was the bus master during the data parity error.
c. The parity error response bit is set in the bridge control.
7
CBFBB_CAP
R
Fast back-to-back capable. The PCI1520 cannot accept fast back-to-back transactions; therefore, bit 7
is hardwired to 0.
6
CB_UDF
R
User-definable feature support. The PCI1520 does not support user-definable features; therefore, bit 6
is hardwired to 0.
5
CB66MHZ
R
66-MHz capable. The PCI1520 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4
–
0
RSVD
R
Reserved. Bits 4
–
0 return 0s when read.
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相關代理商/技術參數(shù)
參數(shù)描述
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