參數(shù)資料
型號(hào): PCI1520-EP
英文描述: Military Enhanced Plastic PC Card Controllers Data Manual
中文描述: 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù): 20/125頁(yè)
文件大?。?/td> 716K
代理商: PCI1520-EP
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2
8
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 2
4. Power Supply Terminals
TERMINAL
NAME
NO.
GHK
I/O
DESCRIPTION
GND
A06, A09, A14,
E01, F19, K01,
P01, R19, W06,
W14
Device ground terminals
VCC
A07, A12, G01,
G19, J19, N01,
N19, W08, W13
Power supply terminal for I/O and internal voltage regulator
VCCA
VCCB
VCCP
VR_EN
P19
Clamp voltage for PC Card A interface. Matches card A signaling environment, 5 V or 3.3 V
R01
Clamp voltage for PC Card B interface. Matches card B signaling environment, 5 V or 3.3 V
A10
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
L01
I
Internal voltage regulator enable. Active-low
VR_PORT
K19
I/O
Internal voltage regulator input/output. When VR_EN is low, the regulator is enabled and this terminal
is an output. An external bypass capacitor is required on this terminal. When VR_EN is high, the regu-
lator is disabled and this terminal is an input for an external 2.5-V core power source.
Table 2
5. PC Card Power Switch Terminals
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GHK
CLOCK
F15
I/O
Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an
input, but can be changed to a PCI1520 output by using bit 27 (P2CCLK) in the system control register (offset 80h, see
Section 4.29). The TPS222X defines the maximum frequency of this signal to be 2 MHz. However, PCI1520 requires a
16-KHz to 100-KHz frequency range. If a system design defines this terminal as an output, then this terminal requires
an external pulldown resistor. The frequency of the PCI1520 output CLOCK is derived from the internal ring oscillator
(16 KHz typical).
DATA
E17
O
Power switch data. DATA is used to communicate socket power control information serially to the power switch.
LATCH
E18
I/O
Power switch latch. LATCH is asserted by the PCI1520 to indicate to the power switch that the data on the DATA line is
valid. When a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4 terminals provide the
serial EEPROM SDA and SCL interface.
Table 2
6. PCI System Terminals
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GHK
GRST
C11
I
Global reset. When the global reset is asserted, the GRST signal causes the PCI1520 to place all output buffers in
a high-impedance state and reset all internal registers. When GRST is asserted, the device is completely in its default
state. For systems that require wake-up from D3, GRST normally is asserted only during initial boot. PRST should
be asserted following initial boot so that PME context is retained during the transition from D3 to D0. For systems
that do not require wake-up from D3, GRST should be tied to PRST.
When the SUSPEND mode is enabled, the device is protected from GRST, and the internal registers are preserved.
All outputs are placed in a high-impedance state.
PCLK
C10
I
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
PRST
C13
I
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1520 to place all output buffers in a
high-impedance state and reset internal registers. When PRST is asserted, the device can generate the PME signal
only if it is enabled. After PRST is deasserted, the PCI1520 is in a default state.
When the SUSPEND mode is enabled, the device is protected from PRST, and the internal registers are preserved.
All outputs are placed in a high-impedance state.
相關(guān)PDF資料
PDF描述
PCI1620GHK Controller Miscellaneous - Datasheet Reference
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
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