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| 型號(hào)： | PCI1520-EP |
| 英文描述： | Military Enhanced Plastic PC Card Controllers Data Manual |
| 中文描述： | 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 22/125頁(yè) |
| 文件大?。?/td> | 716K |
| 代理商： | PCI1520-EP |
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2
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10
Table 2
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8. PCI Interface Control Terminals
TERMINAL
NAME
NO.
GHK
I/O
DESCRIPTION
DEVSEL
F07
I/O
PCI device select. The PCI1520 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the
bus, the PCI1520 monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the
PCI1520 terminates the cycle with an initiator abort.
FRAME
E08
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction
is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus
transaction is in the final data phase.
GNT
B13
I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1520 access to the PCI bus after the current data
transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking
algorithm.
IDSEL
E10
I
Initialization device select. IDSEL selects the PCI1520 during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.
IRDY
B07
I/O
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY
and TRDY are both sampled asserted, wait states are inserted.
PERR
E07
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when
PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).
REQ
A13
O
PCI bus request. REQ is asserted by the PCI1520 to request access to the PCI bus as an initiator.
SERR
C06
O
PCI system error. SERR is an output that is pulsed from the PCI1520 when enabled through bit 8 of the command
register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The PCI1520 need not be the target
of the PCI cycle to assert this signal. When SERR is enabled in the command register, this signal also pulses,
indicating that an address parity error has occurred on a CardBus interface.
STOP
B06
I/O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction.
STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data
transfers.
TRDY
C07
I/O
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both
IRDY and TRDY are asserted, wait states are inserted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI1620GHK | Controller Miscellaneous - Datasheet Reference |
| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
| PCI2050A | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| PCI2050GHK | BUS CONTROLLER |
| PCI2050PDV | BUS CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1520GHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PC CARD CONTROLLERS |
| PCI1520IGHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520IGHKEP | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Mil Enhance PC Card Cntrlr Data Manual RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520IPDV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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