參數(shù)資料
型號： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊
文件頁數(shù)： 30/125頁
文件大?。?/td> 716K
代理商： PCI1520-EP
3
–
2
The power-down sequence is:
1.
Assert GRST to the device to disable the outputs during power down. Output drivers must be powered down
in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping
rails (V
CCA
, V
CCB
, and V
CCP
).
Remove the clamp voltage.
2.
3.
Remove the 3.3-V power from V
CC
.
NOTE:
The clamp voltage can be ramped up or ramped down along with the 3.3-V power. The
voltage difference between V
CC
and the clamp voltage must remain within 3.6 V.
3.2
I/O Characteristics
Figure 3
–
2 shows a 3-state bidirectional buffer. Section 7.2,
Recommended Operating Conditions
, provides the
electrical characteristics of the inputs and outputs.
NOTE:
The PCI1520 meets the ac specifications of the
1997 PC Card Standard
and
PCI Local
Bus Specification.
Tied for Open Drain
OE
Pad
VCCP
Figure 3
–
2. 3-State Bidirectional Buffer
NOTE:
Unused terminals (input or I/O) must be held high or low to prevent them from floating.
3.3
Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI1520 is interfaced with, 3.3 V or 5 V.
The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals.
The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the PCI1520 must reliably accommodate both voltage levels. This is accomplished by using
a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a
5-V PCI bus, then V
CCP
can be connected to a 5-V power supply.
The PCI1520 requires three separate clamping voltages because it supports a wide range of features. The three
voltages are listed and defined in Section 7.2,
Recommended Operating Conditions
. GRST, SUSPEND, PME, and
CSTSCHG are not clamped to any of them.
3.4
Peripheral Component Interconnect (PCI) Interface
The PCI1520 is fully compliant with the
PCI Local Bus Specification
. The PCI1520 provides all required signals for
PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V
CCP
terminal to the desired voltage level. In addition to the mandatory PCI signals, the PCI1520 provides the optional
interrupt signals INTA and INTB.
3.4.1
PCI GRST Signal
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100
μ
s after PCLK
is stable. PRST can be deasserted at the same time as GRST or any time thereafter.
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PDF描述
PCI1620GHK Controller Miscellaneous - Datasheet Reference
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
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