2
–
14
Table 2
–
11. 16-Bit PC Card Interface Control Terminals (Slots A and B) (Continued)
TERMINAL
NUMBER
SLOT
A
NAME
SLOT
B
I/O
DESCRIPTION
GHK
GHK
OE
W15
L03
O
Output enable. OE is driven low by the PCI1520 to enable 16-bit memory PC Card data output during host
memory read cycles.
READY
(IREQ)
H19
V08
I
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate
that the memory card circuits are busy processing a previous write command. READY is driven high when
the 16-bit memory PC Card is ready to accept a new data transfer command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit
I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is
requested.
REG
K14
U07
O
Attribute memory select. REG remains high for all common memory accesses. When REG is asserted,
access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active).
Attribute memory is a separately accessed section of card memory and is generally used to record card
capacity and other configuration and attribute information.
RESET
L15
W05
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
VS1
VS2
J15
L18
U08
P07
I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine
the operating voltage of the PC Card.
WAIT
H18
W09
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle
in progress.
WE
P18
N05
O
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for
memory PC Cards that employ programmable memory technologies.
WP
(IOIS16)
H15
R09
I
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch
on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the
address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that
is addressed is capable of 16-bit accesses.
Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 is A_WE.
Terminal name for slot B is preceded with B_. For example, the full name for terminals 45 and N05 is B_WE.
Table 2
–
12. CardBus PC Card Interface System Terminals (Slots A and B)
TERMINAL
NUMBER
SLOT
A
NAME
SLOT
B
I/O
DESCRIPTION
GHK
GHK
CCLK
M14
P06
O
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All
signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are
sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed
down for power savings.
CCLKRUN
H15
R09
I/O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the PCI1520 to indicate that the CCLK frequency is going to be decreased.
CRST
L15
W05
O
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known
state. When CRST is asserted, all CardBus PC Card signals are placed in a high-impedance state, and
the PCI1520 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but
deassertion must be synchronous to CCLK.
Terminal name for slot A is preceded with A_. For example, the full name for terminals 115 and M14 is A_CCLK.
Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P06 is B_CCLK.