參數(shù)資料
型號： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊
文件頁數(shù)： 42/125頁
文件大?。?/td> 716K
代理商： PCI1520-EP
3
–
14
Table 3
–
7. Register- and Bit-Loading Map
EEPROM
OFFSET
REGISTER
OFFSET
REGISTER BITS LOADED FROM EEPROM
00h
Flag
01h: Load / FFh: do not load
01h
PCI 04h
Command register, bits 8, 6
–
5, 2
–
0
Note: bits loaded per following:
b8
←
b7
b6
←
b6
b5
←
b5
b2
←
b2
b1
←
b1
b0
←
b0
Subsystem vendor ID bits 7
–
0
←
bits 7
–
0
Subsystem vendor ID bits 15
–
8
←
bit 7
–
0
Subsystem ID bits 7
–
0
←
bits 7
–
0
Subsystem ID bits 15
–
8
←
bits 7
–
0
PC Card 16-bit I/F legacy-mode base address bits 7
–
1
←
bits 7
–
1
PC Card 16-bit I/F legacy-mode base address bits 15
–
8
←
bits 7
–
0
PC Card 16-bit I/F legacy-mode base address bit 23:16
←
bit 7:0
PC Card 16-bit I/F legacy-mode base address bits 31
–
24
←
bits 7
–
0
System control bits 7
–
0
←
bits 7
–
0
System control bits 15
–
8
←
bits 7
–
0
System control byte bits 31
–
24
←
bits 7
–
0
Multifunction routing bits 7
–
0
←
bits 7
–
0
Multifunction routing bits 15
–
8
←
bits 7
–
0
Multifunction routing bits 23
–
16
←
bits 7
–
0
Multifunction routing bits 27
–
24
←
bits 3
–
0
Retry status bits 7, 6
←
bits 7, 6
Card control bits 7, 5
←
bits 7, 6
Device control bits 6, 3
–
0
←
bits 6, 3
–
0
Diagnostic bits 7, 4
–
0
←
bits 7, 4
–
0
Power management capabilities bit 15
←
bit 7
ExCA identification and revision bits 7
–
0
←
bits 7
–
0
02h
PCI 40h
03h
PCI 40h
04h
PCI 42h
05h
PCI 42h
06h
PCI 44h
07h
PCI 44h
08h
PCI 44h
09h
PCI 44h
0Ah
PCI 80h
0Bh
PCI 80h
0Ch
PCI 80h
0Dh
PCI 8Ch
0Eh
PCI 8Ch
0Fh
PCI 8Ch
10h
PCI 8Ch
11h
PCI 90h
12h
PCI 91h
13h
PCI 92h
14h
PCI 93h
15h
PCI A2h
16h
ExCA 00h
17h
CB Socket + 0Ch
(function 0)
Function 0 socket force event, bit 27
←
bit 3
18h
CB Socket + 0Ch
(function 1)
Function 1 socket force event, bit 27
←
bit 3
This format must be followed for the PCI1520 to load initializations from a serial EEPROM. All bit fields must be
considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the PCI1520. All hardware address bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit (Figure 3
–
8) assumes the 1010b high-address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
3.6.4
Accessing Serial-Bus Devices Through Software
The PCI1520 provides a programming mechanism to control serial bus devices through software. The programming
is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3
–
8 lists the registers used
to program a serial-bus device through software.
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