參數(shù)資料
型號(hào)： MT16LSDT12864AG-133XX
元件分類(lèi)： DRAM
英文描述： 128M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封裝： MO-161, DIMM-168
文件頁(yè)數(shù)： 5/28頁(yè)
文件大小： 954K
代理商： MT16LSDT12864AG-133XX
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
13
2002 Micron Technology, Inc. All rights reserved.
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
Commands
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. For a more detailed description of commands and oper-
ations, refer to the 512Mb SDRAM component data sheet.
Notes: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.
2. A0–A9, A11 provide column address; A10 HIGH enables the auto-precharge feature (non-
persistent), while A10 LOW disables the auto-precharge feature; BA0–BA1 determine
which device bank is being read from or written to.
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all
device banks are precharged and BA0, BA1 are “Don’t Care.”
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay).
Table 8:
Truth Table – SDRAM Commands and DQMB Operation
CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table
Name (Function)
CS#
RAS# CAS# WE# DQMB
ADDR
DQ
Notes
COMMAND INHIBIT (NOP)
H
XXX
X
NO OPERATION (NOP)
L
HHH
X
ACTIVE (Select bank and activate row)
L
H
X
Bank/Row
X
READ (Select bank and column, and start READ burst)
LHLH
L/H
Bank/Col
X
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L/H
Bank/Col
Valid
BURST TERMINATE
LH
HL
X
Active
PRECHARGE (Deactivate row in bank or banks)
LL
H
L
X
Code
X
AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)
LLL
H
X
4, 5
LOAD MODE REGISTER
LLLL
X
Op-code
X
Write Enable/Output Enable
––––
L
–
Active
Write Inhibit/Output High-Z
––––
H
–
High-Z
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