參數(shù)資料
型號(hào): MT16LSDT12864AG-133XX
元件分類(lèi): DRAM
英文描述: 128M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封裝: MO-161, DIMM-168
文件頁(yè)數(shù): 3/28頁(yè)
文件大?。?/td> 954K
代理商: MT16LSDT12864AG-133XX
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
11
2002 Micron Technology, Inc. All rights reserved.
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
Mode Register Definition
Figure 6:
CAS Latency Diagram
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of the accesses within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in Table 6 on page 10.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in Figure 6. Table 7 on page 12, indicates the operating
frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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