參數(shù)資料
型號(hào): MT16LSDT12864AG-133XX
元件分類: DRAM
英文描述: 128M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封裝: MO-161, DIMM-168
文件頁數(shù): 23/28頁
文件大?。?/td> 954K
代理商: MT16LSDT12864AG-133XX
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
4
2002 Micron Technology, Inc. All rights reserved.
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Table 4 on page 3 for pin number and symbol
information.
Pin Numbers
Symbol
Type
Description
27, 111, 115
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the
command being entered.
42, 79, 125, 163
CK0–CK3
Input
Clock: CK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CK. CK also increments the internal
burst counter and controls the output registers.
63, 128
CKE0, CKE1
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND OPERATION (burst access in progress). CKE is synchronous
except after the device enters power- down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CK, are disabled during power-
down and self refresh modes, providing low standby power.
30, 45,114, 129
S0#–S3#
Input
Chip select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when S# is
registered HIGH. S# is considered part of the command code.
28, 29, 46, 47, 112, 113,
130, 131
DQMB0–
DQMB7
Input
Input/Output mask: DQMB is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked
when DQMB is sampled HIGH during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) when DQMB
is sampled HIGH during a READ cycle.
39, 122
BA0, BA1
Input
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
33–38, 117–121, 123, 126
A0–A12
Input
Address inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective device bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-
code during a MODE REGISTER SET command.
83
SCL
Input
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
165–167
SA0–SA2
Input
Presence-Detect address Inputs: These pins are used to configure the
presence-detect device.
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95,
97–101, 103–104, 139–142,
144, 149–151,
153–156,158–161
DQ0–DQ63
Input/
Output
Data I/O: Data bus.
82
SDA
Input/
Output
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
6, 18, 26, 40, 41, 49, 59, 73,
84, 90, 102, 110, 124, 133,
143, 157, 168
VDD
Supply
Power supply: +3.3V ±0.3V.
1, 12, 23, 32, 43, 54, 64, 68,
78, 85, 96, 107, 116, 127,
138, 148,. 152, 162
VSS
Supply
Ground.
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