參數(shù)資料
型號: MT16LSDT12864AG-133XX
元件分類: DRAM
英文描述: 128M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封裝: MO-161, DIMM-168
文件頁數(shù): 11/28頁
文件大?。?/td> 954K
代理商: MT16LSDT12864AG-133XX
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
19
2002 Micron Technology, Inc. All rights reserved.
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
Notes
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E,
and 7.5ns for -133 after the first clock delay, after the last WRITE is executed. May not
exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -13E, CL = 2 and tCK = 7.5ns; and for -133, CL = 3 and tCK = 7.5ns.
30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
31. Refer to device data sheet for timing waveforms.
32. The value of tRAS used in -13E speed grade modules is calculated from tRC - tRP.
33. Leakage number reflects the worst case leakage possible through the module pin, not
what each memory device contributes.
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