參數(shù)資料
型號(hào): MT16LSDT12864AG-133XX
元件分類: DRAM
英文描述: 128M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封裝: MO-161, DIMM-168
文件頁數(shù): 2/28頁
文件大?。?/td> 954K
代理商: MT16LSDT12864AG-133XX
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
10
2002 Micron Technology, Inc. All rights reserved.
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
Mode Register Definition
Notes: 1. For full-page accesses: y = 2,048.
2. For BL = 2, A1–A9, A11 select the block of two burst; A0 selects the starting column within
the block.
3. For BL = 4, A2–A9, A11 select the block of four burst; A0–A1 select the starting column
within the block.
4. For BL = 8, A3–A9, A11 select the block of eight burst; A0–A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the follow-
ing access wraps within the block.
7. For BL = 1, A0–A9, A11 select the unique column to be accessed, and mode register bit M3
is ignored.
Table 6:
Burst Definition Table
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
00-1
0-1
11-0
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full Page
(y)
n = A0–A9, A11
(location 0-y)
Cn, Cn+1, Cn+2 Cn+3,
Cn+4...
...Cn-1, Cn...
Not Supported
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