參數(shù)資料
型號(hào)： MT16LSDT12864AG-133XX
元件分類(lèi)： DRAM
英文描述： 128M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168
封裝： MO-161, DIMM-168
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 954K
代理商： MT16LSDT12864AG-133XX
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
20
2002 Micron Technology, Inc. All rights reserved.
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
Serial Presence Detect
SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7,
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 9 on page 21).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each sub-
sequent eight bit word. In the read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
Figure 7:
Data Validity
SCL
SDA
Data stable
Data
change
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT16LSDT12864AG-13EC1 功能描述:MODULE SDRAM 1GB 168DIMM RoHS:否 類(lèi)別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM
MT16LSDT1664A 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:8,16 MEG x 64 SDRAM DIMMs
MT16LSDT1664AG-10CC7 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1GBIT 168UDIMM - Trays
MT16LSDT1664AG-10EC1 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1GBIT 168UDIMM - Trays
MT16LSDT1664AG-10EF7 制造商:Micron Technology Inc 功能描述:168-Pin SDRAM DIMMs (x64)
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