General-Purpose Timer Registers
MOTOROLA
Timer Module
11-5
11.5.2
TIMER REFERENCE REGISTERS (TRR0, TRR1)
The TRR is a 16-bit register that contains the reference value that is compared with its respective,
free-running timer counter (TCN), as part of the output-compare function. TRR is a memory-mapped
read/write register.
TRR is set at reset. The reference value is not matched until TCN equals TRR, and the prescaler indicates
that the TCN should be incremented again. Thus, the reference register is matched after (TRR+1) time
intervals.
11.5.3
TIMER CAPTURE REGISTERS (TCR0, TCR1)
The TCR is a 16-bit register that latches the value of the timer counter (TCN) during a capture operation
when an edge occurs on the TIN pin, as programmed in the TMR. TCR appears as a memory-mapped
read-only register and is cleared at reset.
CLK1–CLK0
Input Clock Source for the Timer
11 = TIN pin (falling edge)
10 = Master system clock divided by 16.
Note:
The clock source is synchronized with the timer. However, the divider is not reset to
0 when the timer is stopped, thus successive time-outs may vary slightly in length.
01 = Master system clock
00 = Stops counter. After the counter is stopped, the value in the Timer Counter (TCN)
register remains constant.
RST
The Reset Timer bit performs a software timer reset identical to that of an external
reset. All timer registers take on their corresponding reset values. While this bit is
zero, the other register values can still be written, if necessary. A transition of this
bit from one to zero is what resets the register values. The counter/timer/prescaler
is not clocked unless the timer is enabled.
1 = Enable timer
0 = Reset timer (software reset)
Table 11-4
Timer Reference Register (TRRn)
BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIELD
16-BIT REFERENCE COMPARE VALUE REF15 - REF0
RESET
1
1111
1
R/W
READ/WRITE SUPERVISOR OR USER MODE
ADDR
MBAR+$144, MBAR+$184
Table 11-3 Timer Mode Bit Descriptions (Continued)
BIT NAME
DESCRIPTION
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