9-14
MCF5249UM
MOTOROLA
Interrupt Interface
16
IEC958-2 VALNOGOOD
AUDIO
Validity flag not good on IEC958-2
15
IEC958-2 PARITY ERROR OR SYMBOL ERROR
AUDIO
IEC958-2 receiver parity error or symbol error
14
IEC958-2 U/Q BUFFER ATTENTION
AUDIO
IEC958-2 U/Q channel buffer full interrupt
13
U1CHANRCVOVER
Q1CHANOVERRUN
UQ1CHANERR
AUDIO
IEC958 receiver 1U/Q channel error
12
PDIR1UNOV
AUDIO
processor data in 1 under / over
11
PDIR1RESYN
AUDIO
processor data in 1 resync
10
PDIR2UNOV
AUDIO
Processor data in 2 under / over
9
PDIR2RESYN
AUDIO
Processor data in 2 resync
8
AUDIOTICK
AUDIO
“tick” interrupt
7
U2CHANRCVOVER
Q2CHANOVERRUN
UQ2CHANERR
AUDIO
IEC 958 receiver 2 U/Q channel error
6
PDIR3 RESYNC
AUDIO
Processor data in 3 resync
5
PDIR3 FULL
AUDIO
Processor data in 3 full
4
IIS1TXEMPTY
AUDIO
IIS1 transmit fifo empty
3
IIS2TXEMPTY
AUDIO
IIS2 transmit fifo empty
2
EBUTXEMPTY
AUDIO
ebu transmit fifo empty
1
PDIR2 FULL
AUDIO
Processor data in 2 full
0
PDIR1 FULL
AUDIO
Processor data in 1 full
a.
Set the GPIO_FUNCTION register bit to 1 or 0 for interrupts, as applicable.
b.
This interrupt triggers if an IP bus peripheral generates a Transfer Error Acknowledge interrupt on the IP bus.
This interrupt is used for s/w debug and should not normally be generated. This interrupt maybe generated if for example one of the Audio FIFO 's is
accessed in byte or word mode.
Table 9-23 FlashMedia Interrupt Interface
FLASHMEDIAINTSTAT
FLASHMEDIAINTEN
FLASHMEDIAINTCLEAR BITS
INT NAME
MEANING
RESET
INTERRUPT
ASSOCIATED
INTERRUPT
0
SHIFTBUSY1FALL
interrupt set on falling edge of shift_busy_1
intClear
60
1
SHIFTBUSY1RISE
interrupt set on rising edge of shift_busy_1
intClear
60
2
INTLEVEL1FALL
interrupt set on falling edge of int_level_1
intClear
60
3
INTLEVEL1RISE
interrupt set on rising edge of int_level_1
intClear
60
4
SHIFTBUSY2FALL
interrupt set on falling edge of shift_busy_2
intClear
59
5
SHIFTBUSY2RISE
interrupt set on rising edge of shift_busy_2
intClear
59
6
INTLEVEL2FALL
interrupt set on falling edge of int_level_2
intClear
59
7
INTLEVEL2RISE
interrupt set on rising edge of int_level_2
intClear
59
8
RCV1FULL
interrupt set if receive buffer reg 1 full
read data
58
9
TX1EMPTY
interrupt set if transmit buffer reg 1 empty
write data
58
Table 9-22 Secondary Interrupt Sources (Continued)
INTERRUPT
INTERRUPT NAME
MODULE
DESCRIPTION
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Freescale Semiconductor, Inc.
For More Information On This Product,
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