
MCF5249 Functional Overview
MOTOROLA
Introduction
1-9
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock /
2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.
1.6.16
IDE AND SMARTMEDIA INTERFACES
The MCF5249 system bus allows connection of an IDE hard disk drive and SmartMedia flash card with a
minimum of external hardware. The external hardware consists of bus buffers for address and data and
are intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the
IDE bus. The control signals for the buffers are generated in the MCF5249.
1.6.17
ANALOG/DIGITAL CONVERTER (ADC)
The four channel ADC is based on the Sigma-Delta concept with 12-bit resolution. The digital portion of the
ADC is provided internally. The analog voltage comparator must be provided externally as well as an
external integrator circuit (resistor/capacitor) which is driven by the ADC output. A software interrupt is
provided when the ADC measurement cycle is complete.
1.6.18
FLASH MEMORY CARD INTERFACE
The interface is Sony MemoryStick and SecureDigital compatible. However, there is no hardware support
for MagicGate.
1.6.19
I2C MODULE
The two-wire I2C bus interface, which is compliant with the Philips I2C bus standard, is a bidirectional serial
bus that exchanges data between devices. The I2C bus minimizes the interconnection between devices in
the end system and is best suited for applications that need occasional bursts of rapid communication over
short distances among several devices. Bus capacitance and the number of unique addresses limit the
maximum communication length and the number of devices that can be connected.
1.6.20
CHIP-SELECTS
There are four programmable chip selects on the MCF5249:
Two programmable chip-select outputs (CS0 and CS1) provide signals that enable glueless
connection to external memory and peripheral circuits. The base address, access permissions, and
automatic wait-state insertion are programmable with configuration registers. These signals also
interface to 16-bit ports.
Two dedicated chip selects (CS2 and CS3) are used for the IDE and/or SmartMedia interface
CS0 is active after reset to provide boot-up from external FLASH/ROM.
1.6.21
GPIO INTERFACE
A total of 44 General Purpose inputs and 46 General Purpose outputs are available. These are multiplexed
with various other signals. Eight of the GPIO inputs have edge sensitive interrupt capability.
1.6.22
INTERRUPT CONTROLLER
The MCF5249 has a primary and a secondary interrupt controller. These interrupt controllers handle
interrupts from all internal interrupt sources. In addition, there are 8 GPIOs where external interrupts can
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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