
17-28
MCF5249UM
MOTOROLA
Processor Interface Overview
17.4.5
AUTOMATIC RESYNCHRONIZATION OF FIFOS
An automatic FIFO resynchronization feature is available on the MCF5249. It can be enabled and disabled
separately for every FIFO. If enabled, the hardware will check if the left and right FIFOs are in sync, and if
not, it will set the filling pointer of the right fifo to be equal to the filling pointer of the left fifo.
The operation is shown in
Figure 17-7. Every FIFO auto-resync controller has a state machine with three
states:
1. Off
2. Stand-By
3. On
In the On state, the filling of the left fifo is compared with the filling of right, and if they are not equal, right is
made equal to left, and an interrupt is generated.
Figure 17-7 Automatic Resynchronization FSM of left-right FIFOs
The controller will stay in off state when the feature is disabled. When not disabled, the state machine will
go to the off state on any processor read or write to the FIFO. It will go from On or Off to Standby on any
left sample read from IIS, IIS2, and EBU Tx fifos, or on any left sample write to PDIR1, PDIR2, PDIR3 fifos.
The controller will go from Standby to On on any right sample read from IIS1, IIS2 and EBU Tx fifos, or on
any right sample write to PDIR1, PDIR2 and PDIR3.
Table 17-29 audioGlob Register
BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIELD
PDIR3
FIFO
AUTO
SYNC
AUDIOTICK
SOURCE
EBU2 EXT
EBU1 TX
AUTO
SYNC
IIS2 FIFO
AUTO SYNC
PDIR2
FIFO
AUTO
SYNC
PDIR1
FIFO
AUTO
SYNC
AUDIO_TICK
COUNT
AUDIOTICK
SOURCE
RESET
0
R/W
R/
W
R/
W
R/
W
R/W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
ADDR
0XCC
Off
Standby
On
Read left sample from IIS1, IIS2, EBU
Write left sample to PDIR1, PDIR2
Processor write to IIS1, IIS2, EBU fifo
Processo read from PDIR1, PDIR2
Read left sample from IIS1, IIS2, EBU
Write left sample to PDIR1, PDIR2
Read right sample from IIS1, IIS2, EBU
Write right sample to PDIR1, PDIR2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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