1-6
MCF5249UM
MOTOROLA
MCF5249 Functional Overview
1.6
MCF5249 FUNCTIONAL OVERVIEW
1.6.1
COLDFIRE V2 CORE
The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to
maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage
pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage
operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer
that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,
which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit
(ALU).
1.6.2
DMA CONTROLLER
The MCF5249 provides four fully programmable DMA channels for quick data transfer. Single and dual
address mode is supported with the ability to program bursting and cycle stealing. Data transfer is
selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.
Two internal audio channels and the dual UART can be used with the DMA channels. All channels can
perform memory to memory transfers. The DMA controller has a user-selectable, 24- or 16-bit counter and
a programmable DMA exception handler.
External requests are not supported.
1.6.3
ENHANCED MULTIPLY AND ACCUMULATE MODULE (EMAC)
The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply
instructions in the ColdFire architecture. The EMAC provides functionality in three related areas:
1. Faster signed and unsigned integer multiplies
2. New multiply-accumulate operations supporting signed and unsigned operands
3. New miscellaneous register operations
Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions
for signed and unsigned integers plus signed, fixed-point fractional input operands. The EMAC has a
single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution pipeline.
1.6.4
INSTRUCTION CACHE
The instruction cache improves system performance by providing cached instructions to the execution unit
in a single clock. The MCF5249 processor uses a 8K-byte, direct-mapped instruction cache to achieve 125
MIPS at 140 Mhz. The cache is accessed by physical addresses, where each 16-byte line consists of an
address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit and 8-bit port
sizes to quickly fill cache lines.
1.6.5
INTERNAL 96-KBYTE SRAM
The 96-KByte on-chip SRAM is split over two banks, SRAM0 (64k) and SRAM1 (32K). It provides one
clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or data
segments to maximize performance. Memory in the second bank can be accessed under DMA.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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