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| 型號(hào)： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁(yè)數(shù)： | 75/104頁(yè) |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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6-10
MC92610 SERDES User’s Manual
MOTOROLA
AC Electrical Characteristics
6.3.6
JTAG Test Port Timing
The following Figure 6-10 and Table 6-13 describe the JTAG test port timing.
Table 6-12. Link Differential Input Timing Specification
Symbol
Characteristic
Min
Max
Unit
Tjtol
1, 2
1 Measured between 50-50 percent points.
2 Includes 0.1 UI of band-limited sinusoidal noise, 1.875Mhz < f
noise < 20MHz.
Total jitter tolerance
0.70
-
UI
Tdjtol
Deterministic jitter tolerance
0.36
-
UI
Tdstol
Differential skew tolerance
75
-
ps
Rlat
Receive latency
270
340 3
3 Bit 0 at receiver input to parallel data out, no word synchronization.
bit-times
-400 4
4 Bit 0 at receiver input to parallel data out, single-chip word synchronization.
bit-times
-440 5
5 Bit 0 at receiver input to parallel data out, multi-chip word synchronization.
bit-times
Tacq
Receiver phase acquisition time
-
300 6
6 Measured with worst-case eye opening, Idle pattern, and reference PLL locked.
bit-times
Figure 6-10. JTAG I/O Timing Diagram
TCK
TDO
TDI
TMS
T2
T3
T1
1/fTCK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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