參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 33/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
3-4
MC92610 SERDES User’s Manual
MOTOROLA
Receiver Interface Signals
HSE
Half Speed Enable
Indicates to operate link at half-speed.
Both data and link interfaces run at half
speed.
Input
High
LBE
Loop Back Enable
Activates digital loopback path, such
that the loop-back data from the
transmitter is accepted by the receiver.
Input
High
WSE
Word Synchronization
Enable
Indicates that all four receivers are being
used in unison to receive synchronized
data.
Input
High
WSI
Word Synchronization
Bus Input
Coded word synchronization bus input
that is used to synchronize word timing
between multiple MC92610 devices.
See Section 3.3.4.3 for multi-chip word
synchronization operation.
This signal should be tied high if
multi-chip word synchronization is not
being used.
Input
-
WSO
Word Synchronization
Bus Output
Coded word synchronization bus output
that is used to synchronize word timing
between multiple MC92610 devices.
See Section 3.3.4.3 for multi-chip word
synchronization operation.
Output
-
LME
Link Multiplexer Mode
Enable
Indicates that the data received on
receiver A is presented 16/20 bits wide
on parallel interfaces A and B. Likewise,
the data received on receiver C is
presented 16/20 bits wide on parallel
interfaces C and D.
Input
High
DDRE
Double Data Rate
Enable
When in Link Multiplexer Mode (LME is
high) this signal indicates that the data
interfaces are running at double data
rate.
Input
High
BSYNC
Byte Alignment Mode
Indicates that byte alignment is
employed in the receiver.
Input
High
RCCE
Recovered Clock
Enable
Indicates that the clock frequency
recovered by the receiver is used for the
receiver interface clock (RECV_x_CLK).
Otherwise, the reference clock
frequency is used. This signal is used
with the RECV_REF_A signal to fully
determine clock source.
Input
High
RECV_REF_A
Receiver Interface Clock
Select
Indicates that the clock frequency
recovered by receiver A is used as the
receiver interface clock for all four
receivers. This signal is used with the
RCCE signal to fully determine clock
source.
Input
High
Table 3-1. Receiver Interface Signals (continued)
Signal Name
Description
Function
Direction
Active
State
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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