參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 41/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
MOTOROLA
Chapter 3. Receiver
3-11
Receiver Functional Description
For further details on how the receiver interface is disabled during initial word
synchronization see the note at the end of Section 3.3.3.1, “Byte Alignment and
3.3.4.2
Word Synchronization Bus
Word synchronization information and timing are communicated across the word
synchronization bus. The WSO output drives the bus that is connected to the WSI inputs of
other MC92610 devices with which word synchronization is desired. One of the MC92610
devices is connected as the Leader and the others as the Followers. The Leader’s WSO
output is used to drive its own WSI input and the WSI inputs of all of the Followers. The
WSO output of the Follower devices is not used and is not connected.
NOTE
In order for word synchronization to operate properly in
applications where only one MC92610 is used, the WSI input
must be tied high.
3.3.4.3
Multi-Chip Word Synchronization
Up to four MC92610 devices may be connected to perform multi-word synchronized data
transfer. Configurations of one, two, three and four devices are possible supporting 32-bit,
64-bit, 96-bit and 128-bit wide data transfers. One of the MC92610 devices is connected as
the Leader and the others as the Followers as described in Section 3.3.4.2.
Multi-chip word synchronization uses the same mechanisms for word synchronization as
single-chip word synchronization as described in Section 3.3.4.1. Word synchronization
events must be generated at all concerned transmitters simultaneously in order for
synchronization to be achieved. Word synchronization events must be received at all
receivers within 40 bit-times of each other.
When the Leader device detects a word synchronization event at its receivers, it
communicates the timing of the event to the Follower devices through the Word
Synchronization Bus. The Follower devices use this timing to establish their own word
synchronization relative to the Leader.
Once synchronization is achieved, +6 bit-times of drift between all of the devices’ receivers
is tolerated. If drift exceeds +6 bit-times the devices will continue to operate. However, the
devices will no longer be synchronized properly because they remain locked on the initially
established synchronization.
If any of the devices lose word synchronization, as described in Section 3.3.4.1, all of the
receiving
devices
must
be
forced
to
lose
synchronization
to
ensure
proper
resynchronization. Therefore, system logic should detect loss of word synchronization on
all of the devices by decoding the “Not Word Sync” error. Then the DROP_SYNC should
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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