
MOTOROLA
Chapter 3. Receiver
3-17
Receiver Functional Description
maintain synchronization. If sufficient Idle patterns are not available to drop, receiver
overrun may occur. When overrun occurs, the “overrun/underrun” error is reported as
An overrun error is also reported if ADI mode is disabled and overrun occurs, even if Idles
are available to drop. A sufficient number of Idles must be transmitted to guard against
overrun. The frequency of Idles can be computed based upon the maximum frequency
offset between transmitter and receiver in the system. The number of bytes (characters) that
can be transmitted between Idles is:
(106 / N) - 1 bytes
where: N is the frequency offset in ppm.
In an underrun situation, a byte of data needs to be added in order to maintain
synchronization between the clock domains. The receiver interface adds an Idle byte when
underrun is imminent. However, the Idle is added only if Add/Delete Idle (ADI) mode is
enabled by asserting ADIE. If ADI mode is disabled and underrun occurs, the “overrun/
Codes,” for a one byte clock period.
3.3.8
Half-Speed Mode
Half speed (HS) mode, enabled when HSE is high, operates the receiver in its lower speed
range. In HS mode, the link speed is 1.25 Gbps (1.5625 gigabaud.) The receiver interface
operates at half speed as well, in pace with received data.
3.3.9
Repeater Mode
Repeater mode configures the MC92610 quad device into a 4-link receive-transmit
repeater. In this mode, received data is forwarded to the transmitter for re-transmission.
Link A’s receiver forwards to Link A’s transmitter, Link B’s receiver to Link B’s transmitter
and so on. The receiver’s data outputs and status signals reflect the received data and the
current status of the receiver. See
Section 2.3.1.4 for more information on repeater mode.
3.3.10 Link Multiplexer Mode
Link multiplexer mode configures the MC92610 quad device into a dual transceiver. The
Link multiplexer mode is enabled by asserting LME high. Receivers A and C are active and
are used to receive data. The input circuitry to receivers B and D are disabled and inactive.
The advantage of this mode is that data from a single receiver is demultiplexed onto two
receiver interfaces. Their single data rate (SDR) operation allows full speed link operation
while lowering the parallel interface speeds by one-half.
Data from receiver A is presented on receiver interfaces A and B. Once byte
synchronization is achieved, the first non-Idle character received is output on receiver
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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