參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 63/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
MOTOROLA
Chapter 5. Test Features
5-5
System Accessible Test Modes
that supports this PN equation. Either may be used when inter-operating with another
MC92610 device as long as both devices use the same PN equation.
In addition to using PN equation 2, setting BIST_MODE_SEL high causes the transmitter
to insert 2 Idle characters for every 2048 PN characters transmit. This makes Idles available
to be removed to account for frequency offset between devices. The receiver will properly
handle the inserted Idles when analyzing the PN character stream.
NOTE
For the two Idle characters to be inserted, the ADIE signal must
be asserted. If the ADIE signal is low, the PN Equation 2 is
generated with no inserted Idles.
The total mismatch error count is reset to zero when BIST mode is entered. The count is
updated continuously while in BIST mode. The value of the count is presented on the
receiver interface signals: RECV_x_7 through RECV_x_0, making up the eight-bit error
count, ordered bits 7 through 0, respectively. The value of the count is sticky in that the
count will not wrap to zero upon overflow, but rather, stays at the maximum count value
(11111111).
The RECV_x_ERR, RECV_x_K and RECV_x_IDLE, have special meaning during this
test mode. They report the status of the receiver and PN analysis logic. Table 5-5 describes
the BIST error codes and their meaning.
The BIST sequence makes use of the 8B/10B encoder/decoder. Therefore, this test mode
overrides the setting on TBIE signal and forces Byte Interface mode. The BIST sequence
requires that a normal byte alignment mode be used. The setting of BSYNC is overridden,
forcing the device into the Byte Aligned mode. Also, BIST exercises all transceivers and
their transmission paths, ignoring the setting of LME. Finally, the BIST logic operates at
the reference clock frequency, all received BIST data is synchronized to the reference clock
frequency, overriding the setting of RCCE.
BIST is run at the speed indicated by the frequency of the reference clock and by the speed
range selected by half-speed mode (HSE). The settings of WSE is not altered and BIST will
follow its setting order to properly use this test mode, the system must provide the proper
stimulus in a special sequence. The sequence is as follows:
.
Table 5-5. BIST Error Codes
RECV_x_ERR RECV_x_K
RECV_x_IDLE
Description
Low
BIST running, no PN mismatch this character.
High
Low
BIST running, PN mismatch error this character.
High
Low
High
Receiver byte/word synchronized, PN analyzer is not locked.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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