參數(shù)資料
型號: MC92610VF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝: 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁數(shù): 56/104頁
文件大?。?/td> 1595K
代理商: MC92610VF
MOTOROLA
Chapter 4. System Design Considerations
4-7
Impedance Control Reference Recommendation
minimum and maximum voltages as specified and must have no more than 2 percent
peak-to-peak AC noise. In practice, VREF for the HSTL inputs should track the variations
in the DC value of VDDQ of the sending device for best noise margin. The value of VREF is
to be selected by the user to provide optimum noise margin. Figure 4-2 shows a
recommended circuit topology to generate VREF with recommended ceramic chip filter
capacitor.
4.8.1
Voltage Reference for Single-Ended Reference Clock
Use
The differential reference clock inputs, REF_CLK_P/N, may also be driven by a
single-ended source as described in Section 4.1. The REF_CLK_N input must be set at
VREF for single-ended operation of REF_CLK_P. The REF_CLK_N signal may be
connected to its own reference voltage circuit or may share the reference voltage circuit
used for the HSTL_VREF signal, if board layout allows.
4.9
Impedance Control Reference Recommendation
The MC92610 has an integrated active impedance calibration circuit to ensure the best
possible impedance control of the receiver’s link termination resistors. The calibration
circuit uses an externally established impedance against which internal impedance is
calibrated. The user connects a 250
, 1percent tolerance, resistor between the MC92610
Z_CALIB input and ground. The Z_CALIB input may be tied to GND to disable
impedance calibration, or may be tied to VDD which will set the input impedance to its
maximum value. Figure 4-3 shows an example impedance reference circuit topology.
Figure 4-2. HSTL Class-I VREF Circuit
VDDQ
GND
1.0 F
HSTL_VREF
100
110
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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