參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 51/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
4-2
MC92610 SERDES User’s Manual
MOTOROLA
Startup
REF_CLK_N signal may be connected to its own reference voltage circuit or may share the
reference voltage circuit used for the HSTL_VREF signal, if board layout allows.
4.2
Startup
The MC92610 begins a startup sequence upon application of the reference clock
(REF_CLK_N/P input) to the device. This is considered a cold startup. The cold startup
sequence is as follows:
1. PLL Startup
2. Receiver Initialization and Byte Alignment
3. Word Alignment (if enabled)
4. Run
The expected duration of each step in the startup sequence is shown in Table 4-2. A cold
startup can be initiated at any time by setting RESET low. It is recommended that RESET
be low at initial startup, however, it is not strictly required.
4.3
Repeater Mode
The MC92610 may be configured into a four-link receive-transmit repeater by setting
REPE high. In repeater mode data received on link A's receiver is forwarded to link A's
transmitter, link B's receiver to link B's transmitter and so on. The configuration inputs may
be used to control how the repeater handles the data as it passes through the repeater.
Certain configurations are more effective than others for various applications. The
transmitter at the source, the receiver at the destination and the repeater must have
compatible configurations to ensure proper operation. The following sections describe how
each configuration control affects repeater operation.
4.3.1
Ten-Bit Interface Mode
When the device is in TBI mode (TBIE set high) the internal 8B/10B encoder and decoder
are bypassed and the ten-bit data received is forwarded directly to the transmitter. Running
disparity is assumed correct and is not checked. This is important when using disparity
based word synchronization where incorrect running disparity is used as a word
Table 4-2. Startup Sequence Step Duration
Startup Step
Typical Duration
(in bit times)
Note
PLL Startup
20,480 + 25
s
Receiver Initialization
300
WSE = low
460
WSE = high
Word Alignment
160
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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