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參數(shù)資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 15/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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1-2
MC92610 SERDES User’s Manual
MOTOROLA
Block Diagram
Low power, nominally 1.8W, while operating all transceivers at full speed.
Internal 8B/10B encoder / decoder that can be bypassed for applications where
external coding is used.
Double data rate (DDR), source synchronous, 8-bit and 10-bit HSTL class-1 parallel
data interfaces.
Received data may be clocked at the recovered clock or the reference clock
frequency.
Link-to-link synchronization supports aligned, 32-bit, word transfers. The
synchronization mechanism can tolerates up to 40 bit-times of link-to-link media
delay skew.
Multi-chip link synchronization supports aligned, multi-word transfers. Up to four
MC92610 devices may be used to provide 128-bit, four-word, synchronized
transfers.
Selectable Idle character alignment mode enables aligned transfers with automatic
realignment or unaligned data transfers.
Transceiver links operate over 50
media (100 differential) for lengths of up to
one meter of FR-4 board/backplane or six meters of coax.
Selectable transmit and receive link equalization.
Link inputs have on-chip receiver termination, AC coupling and are “hot swap”
compatible.
Redundant transmitter outputs and receiver inputs are provided. Redundant links are
selectable per transceiver. Broadcast mode enables all transmit link outputs.
Differential reference clock input with single-ended reference clock input option.
Link Multiplexer mode enables operation of two links with single data rate (SDR),
source synchronous, 16-bit and 20-bit parallel data interfaces.
Transceiver channels may be individually disabled.
Repeater mode configures the MC92610 into a four-link receive-transmit repeater.
At speed built-in self test (BIST) for in-system diagnostics.
IEEE 1149.1 JTAG boundary scan test support.
1.3
Block Diagram
The MC92610 is a highly integrated device containing all of the logic needed to facilitate
the application and test of a high-speed serial interface. A block diagram of the MC92610
device is shown in Figure 1-1.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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