參數(shù)資料
型號： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁數(shù)： 38/104頁
文件大小： 1595K
代理商： MC92610VF
MOTOROLA
Chapter 3. Receiver
3-9
Receiver Functional Description
current alignment. Non-Idle characters may be dispersed between the four
misaligned Idles, however, a properly aligned Idle character breaks the sequence.
Alignment is automatically changed to the newly detected alignment without halting
data flow.
Alignment is lost when the number of received characters with 8B/10B coding
errors outnumbers the non-errored characters by four. Credit for non-errored
characters in excess of errored characters is limited to four, such that alignment is
lost after four consecutive errored characters. Misalignment detection of this type is
not available in TBI mode. The receiver restarts its alignment procedure and halts
data flow until a new alignment is established.
Alignment is lost when the DROP_SYNC input is set high for at least two clock
periods. Current alignment is invalidated, the receiver restarts its alignment
procedure and halts data flow until a new alignment is established. DROP_SYNC is
level-sensitive and asynchronous.
When establishing byte alignment, or when data flow is interrupted due to misalignment,
the receiver’s RECV_x_ERR signal is high and the “Not Byte Sync” error is reported as
described in Section 3.3.6.3.
NOTE
During the power up sequence the receiver interface may have
indeterminate data present and the RECV_x_CLK is disabled.
When PLL lock is established the RECV_x_CLK becomes
active and the receiver interface output data is forced to a
negative running K28.5 character (0x17C on bits 9, k,
data[7:0]) until a Byte-Sync is established.
3.3.3.2
Non-Aligned Method
No attempt is made to align the incoming data stream when BSYNC is low. The bits are
simply accumulated into 10-bit characters and forwarded. This mode should be used only
with TBI mode, TBIE set high, and with Word Synchronization disabled, WSE set low.
At system reset and until the MC92610’s system PLL is locked to its reference, the
receiver’s RECV_x_ERR signal is high and the “Not Byte Sync” error is reported, as
described in Section 3.3.6.3. This may seem confusing because no byte synchronization is
performed; but in this mode the status simply indicates that the system PLL has not
achieved lock.
3.3.4
Word Synchronization
The four receivers in the MC92610 can be used cooperatively to receive 32-bit wide aligned
word transfers. Word synchronization is enabled by asserting WSE high. Multiple
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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