參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 40/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
3-10
MC92610 SERDES User’s Manual
MOTOROLA
Receiver Functional Description
MC92610 devices may be used to receive multi-word aligned transfers, through the use of
the word synchronization bus interface.
Word synchronization is possible in Byte or TBI mode. However, word synchronization is
dependent on the detection of simultaneously transmitted word synchronization events that
contain Idle characters. Therefore, if operating in TBI mode, the Idle character must be a
supported member of the code set.
3.3.4.1
Word Synchronization Method
Word synchronization aligns characters in the receiver’s alignment FIFO. Synchronization
is accomplished by lining up word synchronization events detected by each of the receivers,
such that all are coincident at the same stage of their FIFO.
A word synchronization event is defined as four consecutive non-errored Idle (K28.5)
characters followed by at least one non-Idle character.
Word synchronization events must be generated at all concerned transmitters
simultaneously in order for synchronization to be achieved. Word synchronization events
must be received at all receivers within 40 bit-times of each other. Word synchronization is
not attempted until all receivers are byte align locked.
Word synchronization events are used to establish a relationship between the received bytes
in each of the receivers. The bytes of a word are matched and presented simultaneously at
the receiver interface. Once synchronization is achieved the receiver tolerates +6 bit-times
of drift between receivers. If drift exceeds +6 bit-times the receiver will continue to operate.
However, the received bytes will no longer be synchronized properly because the receiver
remains locked on the initially established synchronization. Word synchronization remains
locked until any one of the following three events occur that indicate loss of
synchronization:
Word synchronization lock is lost when one or more of the receivers lose or change byte
alignment. Byte alignment loss is described in Section 3.3.3.1.
Word synchronization lock is lost when overrun/underrun is detected on one or more of the
receivers, see Section 3.3.6.3 for more about overrun/underrun.
Word synchronization lock is lost when explicitly invalidated by asserting DROP_SYNC
high for at least two clocks. When lock is lost, word synchronization must be re-established
before data flow through the receiver resumes.
The receiver interface is disabled during word synchronization. No data is produced at its
outputs until word synchronization is achieved and the first non-Idle character is received.
When establishing word synchronization, or when word synchronization is lost, the
receiver’s RECV_x_ERR signal is high and the “Not Word Sync” error is reported as
described in Section 3.3.6.3.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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