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參數(shù)資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 46/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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3-16
MC92610 SERDES User’s Manual
MOTOROLA
Receiver Functional Description
RCCE is asserted high, then the signal RECV_REF_A is used to select the recovered clock
to be used. If RECV_REF_A is asserted then Channel A’s recovered clock is used for all
four channels. If it is low then each channel uses its own recovered clock.
The receiver interface clock signals, RECV_x_CLK, will always be present when the PLL
is in lock. This is true even if there is no signal present on the serial inputs or if the receiver
has not achieved alignment or byte sync. The frequency of the receiver clock will be the
local reference clock. The clock signals however, are not present during power up or when
the MC92610 is in reset mode and the PLL is not locked.
3.3.7.1Recovered Clock Timing Mode
With RCCE asserted, the recovered clock signal, RECV_x_CLK, is generated by the
receiver and, on average, runs at the reference clock frequency of the transmitter at the other
end of the link. The recovered clock is not generated by a clock recovery PLL, but is
generated by the receiver bit-accumulation and byte-alignment logic.
In order to track a transmitter frequency that is offset from the receiver’s reference clock
frequency, the duty cycle and period of the recovered clock is modulated. The MC92610 is
designed to tolerate up to a 200 ppm of frequency offset. The recovered clock duty cycle
may be reduced or increased (by 200 ps, if the nominal frequency is 156.25 Mhz) in order
to match the transmitter frequency.
For example: If the transmitter is sending data at a rate faster than the receiver, then a
shortened cycle is generated as needed to track the incoming data rate. Alternately, if the
transmitter is running slower than the receiver, then a long cycle is generated.
All receiver channel outputs are source synchronous with their respective RECV_x_CLK
outputs. If the receivers are being operated in word synchronization mode (WSE = high),
the data for all four receivers are timed relative to link A’s recovered clock RECV_A_CLK.
In word synchronization all four clocks are derived from channel A and may be used if
necessary.
3.3.7.2
Reference Clock Timing Mode
Data is timed relative to the local reference clock frequency when RCCE is low.
Synchronization between the recovered clock and the reference clock is handled by the
receiver interface. Frequency offset between the transmitter’s reference clock and the
receiver’s reference clock causes overrun/underrun situations. Overrun occurs when the
transmitter is running faster than the receiver. Underrun occurs when the transmitter is
running slower than the receiver.
In an overrun situation, a byte of data needs to be dropped in order to maintain
synchronization between the clock domains. The receiver interface searches for an Idle byte
to drop when overrun is imminent. However, the Idle is dropped only if Add/Delete Idle
(ADI) mode is enabled by asserting ADIE. When enabled, Idle patterns are dropped to
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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