11/3/95
SECTION 1: OVERVIEW
UM Rev 1
MOTOROLA
MC68349 USER'S MANUAL
xi
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
5.8.3.11
Conditional Branch Instructions ..................................................... 5-102
5.8.3.12
Control Instructions ........................................................................ 5-103
5.8.3.13
Exception-Related Instructions and Operations............................. 5-104
5.8.3.14
Save and Restore Operations........................................................ 5-105
Section 6
Quad Data Memory Module
6.1
Functional Description ........................................................................... 6-1
6.2
Application Areas .................................................................................. 6-2
6.3
Programming Model .............................................................................. 6-2
6.3.1
Module Configuration Register (MCR) .............................................. 6-3
6.3.2
QDMM Base Address Registers (QBAR3–QBAR0) .......................... 6-4
Section 7
DMA Controller Module
7.1
DMA Module Overview ......................................................................... 7-2
7.2
DMA Module Signal Definitions............................................................. 7-4
7.2.1
DMA Request (DREQ1 , DREQ2 ) ...................................................... 7-4
7.2.2
DMA Acknowledge (DACK1, DACK2) ............................................... 7-4
7.2.3
DMA Done (DONE1 , DONE2 ) ........................................................... 7-4
7.3
Transfer Request Generation................................................................ 7-4
7.3.1
Internal Request Generation ............................................................. 7-4
7.3.1.1
Internal Request, Maximum Rate................................................... 7-5
7.3.1.2
Internal Request, Limited Rate ...................................................... 7-5
7.3.2
External Request Generation ............................................................ 7-5
7.3.2.1
External Burst Mode ...................................................................... 7-5
7.3.2.2
External Cycle Steal Mode............................................................. 7-5
7.3.2.3
External Request with Other Modules ........................................... 7-6
7.4
Data Transfer modes ............................................................................ 7-7
7.4.1
Single-Address Mode ........................................................................ 7-7
7.4.1.1
Single-Address Read ..................................................................... 7-7
7.4.1.2
Single-Address Write ..................................................................... 7-10
7.4.2
Dual-Address Mode ........................................................................... 7-12
7.4.2.1
Dual-Address Read ........................................................................ 7-12
7.4.2.2
Dual-Address Write ........................................................................ 7-15
7.5
Bus Arbitration ....................................................................................... 7-18
7.6
DMA Channel Operation ....................................................................... 7-18
7.6.1
Channel Initialization and Startup ...................................................... 7-18
7.6.2
Data Transfers ................................................................................... 7-19
7.6.2.1
Internal Request Transfers ............................................................ 7-19
7.6.2.2
External Request Transfers ........................................................... 7-19
7.6.3
Channel Termination ......................................................................... 7-20