11/3/95
SECTION 1: OVERVIEW
UM Rev.1.0
iv
MC68349 USER’S MANUAL
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
2.5.1
Reset (RESET) .................................................................................. 2-6
2.5.2
Bus Error (BERR ) .............................................................................. 2-6
2.6
Chip Selects (CS3–CS0) ....................................................................... 2-6
2.7
Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3) ............................... 2-7
2.8
Bus Control Signals............................................................................... 2-7
2.8.1
Address Strobe (AS) ......................................................................... 2-7
2.8.2
Data Strobe (DS ) ............................................................................... 2-7
2.8.3
Read/Write (R/W) .............................................................................. 2-7
2.8.4
Transfer Size (SIZ1, SIZ0) ................................................................ 2-7
2.8.5
Data and Size Acknowledge (DSACK1, DSACK0 ) ............................ 2-8
2.9
Bus Arbitration Signals.......................................................................... 2-8
2.9.1
Bus Request (BR) .............................................................................. 2-8
2.9.2
Bus Grant (BG ) .................................................................................. 2-8
2.9.3
Bus Grant Acknowledge (BGACK) .................................................... 2-8
2.9.4
Read-Modify-Write Cycle (RMC) ....................................................... 2-9
2.10
Clock Signals ........................................................................................ 2-9
2.10.1
System Clock (CLKOUT)................................................................... 2-9
2.10.2
Crystal Oscillator (EXTAL) ................................................................ 2-9
2.10.3
External Filter Capacitor (XFC) ......................................................... 2-9
2.10.4
Clock Mode Select (MODCK) ............................................................ 2-9
2.11
Test Signals .......................................................................................... 2-10
2.11.1
Test Cock (TCK)................................................................................ 2-10
2.11.2
Test Mode Select (TMS) ................................................................... 2-10
2.11.3
Test Data In (TDI) .............................................................................. 2-10
2.11.4
Test Data Out (TDO) ......................................................................... 2-10
2.12
Debug and Emulation Support Signals ................................................. 2-10
2.12.1
Breakpoint (BKPT ) ............................................................................ 2-10
2.12.2
Freeze (FREEZE) .............................................................................. 2-10
2.12.3
Instruction Pipe (IPIPE0, IPIPE1) ...................................................... 2-11
2.13
DMA Module Signals ............................................................................ 2-11
2.13.1
DMA Request (DREQ2, DREQ1 ) ...................................................... 2-11
2.13.2
DMA Acknowledge (DACK2, DACK1) ............................................... 2-11
2.13.3
DMA Done (DONE2, DONE1 ) ........................................................... 2-12
2.14
SERIAL Module Signals........................................................................ 2-12
2.14.1
Serial External Clock Input (SCLK) ................................................... 2-12
2.14.2
Serial Crystal Oscillator (X1, X2) ....................................................... 2-12
2.14.3
Receive Data (RxDA, RxDB) ............................................................. 2-12
2.14.4
Transmit Data (TxDA, TxDB)............................................................. 2-12
2.14.5
Receiver Ready ( R≈RDYA) ............................................................... 2-12
2.14.6
Transmitter Ready (T≈RDYA )............................................................ 2-13
2.14.7
Request to Send ( RTSA, RTSB) ....................................................... 2-13
2.14.8
Clear to Send (CTSA, CTSB) ............................................................ 2-13