INDEX- 4
MC68349 USER’S MANUAL
MOTOROLA
Vector, 5-28, 5-36, 5-53
EXTAL 2-9, 10-1
External Bus Interface, 1-7, 4-18, 4-37
EXTEST 9-10
— F —
Fast Termination, 1-8, 3-22, 7-20, 7-21
Fault, 5-44
Address Register, 5-57
Double Bus ,3-52
Recovery ,5-42
Types, 5-45, 5-46
Double Bus Fault, 4-6
FCx Signals, 2-5, 3-3
Features (of the MC68349), 1-2
Fetch Effective Address Timing Table, 5-92
FFULLA Signals ,2-13, 8-8
FIFO Stack, 8-13
FIFO Full Indicator, 8-7
Fill Memory Block Command (FILL), 5-73
F-line Instructions, 5-37
Flowchart,
Breakpoint Operation, 3-35
Bus Arbitration for Single Request, 3-54
Byte Read Cycle, 3-24
Interrupt Acknowledge Cycle, 3-39
Long Word Write Cycle, 3-28
Long-Word Read Cycle, 3-24
Reset Operation, 5-33
Serial Module Programming, 8-43
FORCE_BGND, 5-62
Format Error, 5-36 5-41
Four-Word Stack Frame, 5-50
Framing Error, 8-11
FREEZE Signal, 2-10, 4-3, 4-21, 5-57, 5-62
Frequency Divider, 4-13
Function Code Register (FCR), 7-30
— G —
GND, 2-14
GO, 5-59, 5-66
— H —
Halt Operation, 3-50
HALT Signal, 2-6, 3-21, 3-43, 3-47, 3-50
Handshake Signals, 3-20, 7-7
Hardware Breakpoint, 5-29, 5-32, 5-36, 5-50
HI-Z Instruction, 9-10
— I —
IACK7– IACK1 Signals, 2-5
Identification Register (IDR), 4-26
IEEE 1149.1, 1-8, 9-1
AC Electrical Specifications, 11-22
Boundary Scan Register, 9-3
Bypass Register, 9-11
Instructions, 9-10
LPSTOP, 9-12
Non-IEEE 1149.1 Operation, 9-12
IFETCH Signals, 2-11, 5-54, 5-59, 5-78, 5-80
Illegal Instruction, 5-37
Immediate Arithmetic/logic Instruction Table, 5-97
Initialization, 4-39
Input Port Change Register (IPCR), 8-25
Input Port Register (IP), 8-26
Instruction(s),
Execution Overlap, 5-83, 5-84
Execution Time Calculation, 5-84
Execution Timing, 5-80
LINK Instruction, 5-25
LPSTOP Instruction, 5-18
No Operation (NOP) Instruction, 5-25
Pipeline, 5-81, 5-82
Prefetch, 3-45, 5-82
Register, 5-78
Set, 5-16
TBL Instruction, 5-18
Timing, 5-87, 5-90
UNLK Instruction, 5-25
Intermodule Bus, 1-5, 4-6, 5-1, 5-6, 5-8, 6-1, 8-1,
8-17
Internal Bus Monitor, 3-5, 3-59, 4-4, 4-6
Internal Exception, 5-30
Interrupt(s), 1-8, 5-30, 7-20
Acknowledge Cycle, 3-38, 3-41, 4-6, 8-17
Enable Register (IER), 8-4, 8-7, 8-27
Exceptions, 5-30
Level Register (ILR), 8-28
Nonmaskable Interrupts, 5-41
Register (INTR), 7-31
Request Lines, 2-6, 2-7
Service Mask, 7-2
Simultaneous, 4-9
Spurious Interrupt, 3-41