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MC68349 USER'S MANUAL
MOTOROLA
fault monitor can reset the processor. The software watchdog timer can pull the processor
out of an infinite loop. A periodic interrupt timer can be sent to the CPU32+ for dynamic
random access memory (DRAM) refresh, time-of-day clock, task switching, etc.
1.4.3.3 CLOCK SYNTHESIZER. The clock synthesizer generates the clock signals used
by all internal operations as well as a clock output used by external devices. The clock
synthesizer can operate with an inexpensive 32.768-kHz watch crystal or an external
oscillator for reference, using an internal phase-locked loop and voltage-controlled
oscillator. At any time, software can select clock frequencies from 131 kHz to the
maximum frequency rate, favoring either low power consumption or high performance.
Alternately, an external clock can drive the clock signal directly at the operating frequency.
With its fully static high-density complimentary metal oxide semiconductor (HCMOS)
design, it is possible to completely stop the system clock without losing the contents of the
internal registers.
1.4.3.4 CHIP SELECT AND WAIT STATE GENERATION. Four programmable chip
selects provide signals to enable external memory and peripheral circuits. Address space
and write protection can be selected for each. The block size can be selected from 256
bytes up to 4 Gbytes in increments of 2n. Accesses can be preselected for either 8-, 16-,
or 32-bit transfers. Fast synchronous termination or up to six wait states can be
programmed. External handshakes can also signal the end of a bus transfer. A system
can boot from reset out of 8-, 16- , or 32-bit-wide memory.
1.4.3.5 INTERRUPT HANDLING. Up to seven discrete interrupt inputs are available for
external interrupt sources. Each interrupt can be configured to either autovector to an
interrupt handler or generate an external interrupt acknowledge to allow the external
device to provide the handler vector. Decoded interrupt acknowledge signals are also
available for each interrupt input.
1.4.3.6 DISCRETE I/O PINS. When not used for other functions, 16 pins can be
programmed as discrete input or output signals. Additionally, in other peripheral modules,
pins for otherwise unused functions can often be used for general input/output.
1.4.3.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68349
includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1
standard for boundary scan testability, often referred to as JTAG (Joint Test Action
Group).
1.5 POWER MANAGEMENT
Power consumption on the M68300 family parts is low overall because more of a system's
circuitry is on a single piece of silicon, minimizing capacitances and buffering. The
MC68349V operates from a 3.3-V power source, saving over 50% of the power required
to operate the 5-V MC68349. The MC68349 is implemented in a low-power HCMOS
process, assuring high performance with low power consumption. All circuits on the
MC68349 are implemented using static circuits, maintaining stable operation for clocking
frequencies down to zero.