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MC68349 USER'S MANUAL
MOTOROLA
communication between these modules is fully synchronized and that arbitration and
interrupts can be handled in parallel with data transfers, greatly improving system
performance. The IMB on the MC68349 is 32 bits wide, allowing transfers of 32 bits of
data in a single bus cycle. Internal accesses across the IMB may be monitored from
outside the chip, if desired.
Each module operates independently. Modules and their registers are accessed in the
memory map of the CPU32+ (and DMA) for easy access by general M68000 instructions.
Each module may be assigned its own interrupt level, response vector, and arbitration
priority. Since each module is a self-contained design and adheres to the IMB interface
specifications, the modules may appear on other M68300 family products, retaining the
investment in the software drivers for the module.
1.4.1 Direct Memory Access Module
The MC68349 contains a high-speed 32-bit DMA controller, used to quickly move large
blocks of data between internal peripherals, external peripherals, or memory without
processor intervention. With the MC68349's 32-bit wide external bus, this is an excellent
high performance DMA controller to work in many 32-bit microprocessor systems. The
DMA module consists of two independent programmable channels. Each channel has
separate request, acknowledge, and done signals. Each channel can operate in either
single-address (flyby) or dual-address mode and supports 32 bits of address and 8-, 16-,
or 32-bit data transfers.
In single-address mode, only one address (the source or the destination) is provided, and
a peripheral device such as a serial communications controller receives or supplies the
data. An external request must start a single-address transfer.
In dual-address mode, two bus transfers occur, one from a source device and the other to
a destination device. Dual-address transfers can be started by either an internal or
external request. The source and destination port size can be selected independently.
Byte, word, and long-word counts up to 32 bits can be transferred. All addresses and
transfer counters are 32 bits. The DMA channels support both burst and cycle steal
external request modes. Internal requests can be programmed to occupy form 25 to 100
percent of the data bus bandwidth. The DMA controller can be configured in all modes to
release the bus back to the CPU when a high-priority interrupt occurs.
The DMA module can sustain a transfer rate of 25 Mbytes/sec in dual-address mode and
50 Mbytes/sec in single-address mode @ 25.16 MHz (8.4 and 33.3 Mbytes/sec @ 16.78
MHz). The DMA controller and CPU32+ arbitrate for the bus in parallel with existing bus
cycles, typically eliminating all bus arbitration overhead and allowing DMA and CPU bus
cycles to occur back-to-back without intervening idle clocks. Three-clock and slower DMA
transfers have no arbitration overhead; some fast termination DMA transfers incur a single
idle clock before the next CPU access.