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11/3/95
SECTION 1: OVERVIEW
UM Rev.1.0
xviii
MC68349 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure
Page
Number
Title
Number
5-26
Debug Serial I/O Block Diagram .................................................................. 5-60
5-27
Serial Interface Timing Diagram .................................................................. 5-61
5-28
BKPT Timing for Single Bus Cycle .............................................................. 5-62
5-29
BKPT Timing for Forcing BDM ..................................................................... 5-62
5-30
BKPT /DSCLK Logic Diagram....................................................................... 5-63
5-31
Command Sequence Diagram .................................................................... 5-65
5-32
Functional Model of Instruction Pipeline ...................................................... 5-79
5-33
Instruction Pipeline Timing Diagram ............................................................ 5-80
5-34
Block Diagram of Independent Resources .................................................. 5-81
5-35
Simultaneous Instruction Execution ............................................................. 5-83
5-36
Attributed Instruction Times ......................................................................... 5-83
5-37
Example 1—Instruction Stream ................................................................... 5-87
5-38
Example 2—Branch Taken .......................................................................... 5-88
5-39
Example 2—Branch Not Taken.................................................................... 5-88
5-40
Example 3—Branch Negative Tail ............................................................... 5-89
6-1
Programming Model for the QDMM ............................................................. 6-2
7-1
DMA Block Diagram ..................................................................................... 7-1
7-2
Single-Address Transfers............................................................................. 7-3
7-3
Dual-Address Transfer ................................................................................. 7-3
7-4
DMA External Connections to Serial Module ............................................... 7-6
7-5
Single-Address Read Timing (External Burst) ............................................. 7-8
7-6
Single-Address Read Timing (Cycle Steal) .................................................. 7-9
7-7
Single-Address Write Timing (External Burst) ............................................. 7-10
7-8
Single-Address Write Timing (Cycle Steal) .................................................. 7-11
7-9
Dual Address Read Timing (External Burst—Source Requesting) .............. 7-13
7-10
Dual-Address Read Timing (Cycle Steal–Source Requesting) .................... 7-14
7-11
Dual Address Write Timing (External Burst—Destination Requesting)........ 7-16
7-12
Dual Address Write Timing (Cycle Steal—Destination Requesting) ............ 7-17
7-13
Fast Termination Option Timing (Cycle Steal) ............................................. 7-21
7-14
Fast Termination Option Timing (External Burst—Source Requesting) ...... 7-22
7-15
DMA Module Programming Model ............................................................... 7-23
7-16
Packing and Unpacking of Operands........................................................... 7-35
8-1
Simplified Block Diagram ............................................................................. 8-1
8-2
External and Internal Interface Signals ........................................................ 8-5
8-3
Baud Rate Generator Block Diagram........................................................... 8-8
8-4
Transmitter and Receiver Functional Diagram ............................................ 8-9
8-5
Transmitter Timing Diagram ........................................................................ 8-10
8-6
Receiver Timing Diagram............................................................................. 8-12
8-7
Looping Modes Functional Diagram ............................................................ 8-15