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參數(shù)資料
| 型號： | M5M4V4S40CTP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 27/45頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | M5M4V4S40CTP-12 |
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27
M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70°C, unless otherwise noted)
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
NOTES:
1. VIH (max) = 5.75V for pulse width less than 5ns.
2. VIL (min) = -1.0V for pulse width less than 5ns.
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ 5.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ 4.6
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25 °C
1000
mW
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-65 ~ 150
°C
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VddQ
Supply Voltage for Output
3.0
3.3
3.6
V
VssQ
Supply Voltage for Output
0
0
0
V
VIH*1
High-Level Input Voltage all inputs
2.0
5.5
V
VIL*2
Low-Level Input Voltage all inputs
-0.3
0.8
V
Symbol
Parameter
Test Condition
Limits (max.)
Unit
CI(A)
Input Capacitance, address pin
5
pF
CI(C)
Input Capacitance, control pin
VI=Vss
f=1MHz
Vi=25mVrms
5
pF
CI(K)
Input Capacitance, CLK pin
5
pF
CI/O
Input Capacitance, I/O pin
7
pF
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