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參數(shù)資料
| 型號： | M5M4V4S40CTP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 17/45頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | M5M4V4S40CTP-12 |
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17
M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
WRITE
A WRITE command can be issued after tRCD from the bank activation (ACT). Input data is written to the
SDRAM beginning on the rising edge of CLK in the same cycle that the WRITE command is applied.
The remaining input data will be clocked in on the subsequent CLK cycles. The number of writes depends
on the BL set in the mode register. The start address is specified by A7-0 and the address sequence is
defined by the Burst Type. A WRITE command may be applied to any active bank. This allows the row
precharge time (tRP) to be hidden behind continuous input data. Write recovery time (tWR) is required
between the last write and subsequent precharge (PRE) inside of a bank.
When A8 is high during a WRITE command (WRITEA) , an auto precharge is performed after the last data
is input. All commands (READ, WRITE, PRE, ACT) to the same bank are inhibited until the internal
precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT
command can be issued after tRP. WRITEA
cannot
be used for FP burst length operations.
The Mode Register can be programmed for burst read and single write. In this mode the write data is only
clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data
burst length is unaffected while in this mode.
Dual Bank Interleaving WRITE (BL=4)
CLK
Command
A0-7
A8
BA
DQ
ACT
Xa
Xa
0
Write
Y
0
0
Write
Y
0
1
Da0
Da1
Da2
Da3
ACT
Xb
Xb
1
PRE
0
0
tRCD
Burst Length
Db0
Db1
Db2
Db3
tRCD
tWR
WRITE with Auto-Precharge (BL=4)
CLK
Command
A0-7
A8
BA
DQ
ACT
Xa
Xa
0
Write
Y
1
0
Da0
Da1
Da2
Da3
ACT
Xa
Xa
0
Internal precharge begins
tRCD
tRP
tWR
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M5M4V4S40CTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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