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參數(shù)資料
| 型號： | M5M4V4S40CTP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 21/45頁 |
| 文件大小： | 1458K |
| 代理商： | M5M4V4S40CTP-12 |
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21
M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
[ Write Interrupted by Write ]
A burst write operation can be interrupted by a new write to the same or opposite bank. Random column
access is allowed. WRITE to WRITE interval is a minimum of one CLK.
[ Write Interrupted by Read ]
A burst write operation can be interrupted by a read of the same or opposite bank. Random column access
is allowed. WRITE to READ interval is a minimum of one CLK. The input data on DQ at the interrupting
READ cycle is "don’t care".
Write Interrupted by Write (BL=4)
CLK
Command
A0-7
A8
BA
DQ
Write
Yi
0
0
Write
Yk
0
1
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
0
Dbk1 Dbk2
Write
Yl
0
0
Dal0
Dal1
Dal2
Dal3
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-7
A8
BA
DQ
Write
Yi
0
0
Qaj0
READ
Yj
0
0
Qaj1
Dai0
Dak0 Dak1
DQMU
DQML
Write
Yk
0
0
READ
Yl
0
1
Qbl0
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| M5M4V4S40CTP-15 | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V4S40CTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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