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參數(shù)資料
| 型號： | M5M4V4S40CTP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 1/45頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | M5M4V4S40CTP-12 |
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M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
DESCRIPTION
The M5M4V4S40CTP is a 2-bank x 131,072-word x 16-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
M5M4V4S40CTP achieves very high speed data rates up to
83MHz, and is suitable for main memory or graphic memory
in computer systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 83MHz / 67MHz
- Fully synchronous operation referenced to clock rising edge
- Dual bank operation controlled by BA(Bank Address)
- /CAS latency- 1/2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Sequential and interleave burst (programmable)
- Byte control by DQMU and DQML
- Random column access
- Auto precharge / All bank precharge controlled by A8
- Auto and self refresh
- 1024 refresh cycles /16.4ms
- LVTTL Interface
- 400-mil, 50-pin Thin Small Outline Package
(TSOP II) with 0.8mm lead pitch
CLK : Master Clock
CKE : Clock Enable
/CS : Chip Select
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ0-15 : Data I/O
DQMU : Upper Output Disable/ Write Mask
DQML : Lower Output Disable/ Write Mask
A0-8 : Address Input
BA : Bank Address
Vdd : Power Supply
VddQ : Power Supply for Output
Vss : Ground
VssQ : Ground for Output
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Vdd
DQ0
DQ1
VssQ
DQ2
DQ3
VddQ
DQ4
DQ5
/WE
/CAS
/RAS
/CS
BA
A8
A0
A1
A2
A3
Vdd
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
VddQ
DQ11
DQ10
NC
DQMU
CLK
CKE
NC
NC
NC
A7
A6
A5
A4
Vss
PIN CONFIGURATION
(TOP VIEW)
DQML
VddQ
VddQ
DQ7
DQ8
DQ6
DQ9
VssQ
VssQ
Max.
Frequency
CLK Access
Time
M5M4V4S40CTP-12
83MHz
8ns
M5M4V4S40CTP-15
67MHz
9ns
PRELIMINARY
Some of contents are described for general products
and are subject to change without notice.
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| M5M4V4S40CTP-15 | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
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| M5M4V64S30ATP-10 | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| M5M4V64S30ATP-12 | 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM |
| M5M4V64S30ATP-8 | 30V N-Channel PowerTrench MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V4S40CTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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