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參數(shù)資料
| 型號： | M5M4V4S40CTP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 12/45頁 |
| 文件大小： | 1458K |
| 代理商： | M5M4V4S40CTP-12 |
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12
M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
POWER ON SEQUENCE
Before starting normal operations, the following power on sequence is necessary to prevent the SDRAM
from damage and malfunctions.
1. Apply power and start the clock, CLK. Attempt to maintain CKE high, DQMU/DQML high and NOP
conditions on the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500μs.
3. Issue precharge commands for all banks (PRE or PREA).
4. After all banks reach an idle state and after the row the precharge time (tRP) issue 8 or more auto-refresh
commands.
5. Finally, issue a mode register set (MRS) command to initialize the mode register.
After tRSC from the MRS command, the SDRAM will be in an idle state and ready for normal operations.
MODE REGISTER
Burst Length, Burst Type, and /CAS Latency can be programmed by setting the mode register (MRS). The
mode register stores this data until the next MRS command. An MRS command can only be issued when
both banks are idle. After tRSC from an MRS operation, the SDRAM is ready for new commands.
R is Reserved for Future Use
F.P. = Full Page (256)
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 X X
LATENCY
MODE
/CAS LATENCY
R
1
2
3
R
OP
0 0
0 1
1 0
1 1
R
Burst read / Single write
R
Burst read / Burst write
OPCODE
BA
A8
A7
A6
A5
A4
A3
A2
A1
A0
LTMODE
BT
BL
OPCODE
0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0
1
2
4
8
R
R
R
F.P.
BT= 1
1
2
4
8
R
R
R
R
/CS
/RAS
/CAS
/WE
BA, A8 -A0
CLK
V
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| M5M4V4S40CTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
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| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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