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參數(shù)資料
| 型號： | M5M4V4S40CTP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| 中文描述： | 4分（2 -銀行甲131072字x 16位）同步DRAM |
| 文件頁數(shù)： | 22/45頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | M5M4V4S40CTP-12 |
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M5M4V4S40CTP-12, -15
Feb ‘97
Preliminary
MITSUBISHI LSIs
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 0.3)
[ Write Interrupted by Precharge ]
A burst write operation can be interrupted by precharging (PRE) the same bank. Write recovery time
(tWR) is required between the last input data and the next PRE. This may require DQMU/DQML control
depending on the CLK frequency and tWR timing. See the example below.
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this case, the
write recovery time is not required and the bank remains active (Please see the waveforms below). The
WRITE to TERM minimum interval is one CLK.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-7
A8
BA
DQ
Write
Yi
0
PRE
0
Dai0
Dai1
DQMU
DQML
ACT
Xb
Xb
0
0
0
tWR
tRP
This data should be masked to satisfy tWR requirement.
Write Interrupted by Burst Terminate (BL=4)
CLK
Command
A0-7
A8
BA
DQ
Write
Yi
0
0
TERM
Dai0
Dai1
DQMU
DQML
Dai2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V4S40CTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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