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型號：	M32185F4VFP
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)：	78/1032頁
文件大?。?/td>	5750K
代理商：	M32185F4VFP

INTERRUPT CONTROLLER (ICU)

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

5.5 Description of Interrupt Operation

[6] Enabling multiple interrupts

To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling

multiple interrupts), set the PSW register IE bit to "1."

Notes: There are precautions to be taken when reenabling interrupts (by setting the IE bit to

"1") after reading the Interrupt Vector Register (IVECT). For details, see the Section

5.2.1, "Interrupt Vector Register (IVECT)." The precautions apply to the Process [4],

therefore, other processes are not required to add.

There are precautions to be taken when reenabling interrupts (by setting the IE bit to

"1") after writing to the Interrupt Request Mask Register (IMASK). For details, see the

Section 5.2.2, "Interrupt Request Mask Register (IMASK)."

[7] Branching to the internal peripheral I/O interrupt handler

Branch to the start address of the interrupt handler that was read out in [5].

[8] Processing in the internal peripheral I/O interrupt handler

[9] Disabling interrupts

Clear the PSW register IE bit to "0" to disable interrupts.

[10] Restoring the Interrupt Request Mask Register (IMASK)

Restore the Interrupt Request Mask Register that was saved to the stack in [2].

[11] Restoring registers from the stack

Restore the registers that were saved to the stack in [1].

[12] Completion of external interrupt processing

Execute the RTE instruction to complete the external interrupt processing. The program returns

to the state in which it was before the interrupt request currently being processed was accepted.

(3) Identifying the source of the interrupt request generated

If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request

Status Register provided for each internal peripheral I/O to identify the source of the interrupt request

(4) Enabling multiple interrupts

To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to

enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save

each register (BPC, PSW, general-purpose registers and IMASK) to the stack.

Note: Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the

ICU vector table, as shown in Figure 5.5.2, "Typical Handler Operation for Interrupts from

Internal Peripheral I/O."

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