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型號(hào)：	M32185F4VFP
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	17/1032頁(yè)
文件大?。?/td>	5750K
代理商：	M32185F4VFP

SUMMARY OF PRECAUTIONS

Appendix 4

Appendix 4-22

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Appendix 4.10 Notes on A/D Converter

Appendix Figure 4.10.1 Internal Equivalent Circuit of the Analog Input Part

Appendix 4.10 Notes on A/D Converter

Forcible termination during scan operation

If A/D conversion is forcibly terminated by setting the A/D conversion stop bit (ADCSTP) to "1" during scan mode

operation and the A/D data register for the channel that was in the middle of conversion is accessed for read, the

read value shows the last conversion result that had been transferred to the data register before the conversion was

forcibly terminated.

Modification of the A/D converter related registers

If the content of any register—A/D Conversion Interrupt Control Register, Single or Scan Mode Registers or A/D

Successive Approximation Register, except the A/D conversion stop bit—is modified in the middle of A/D conver-

sion, the conversion result cannot be guaranteed. Therefore, do not modify the contents of these registers while A/D

conversion is in progress, or be sure to restart A/D conversion if register contents have been modified.

Handling of analog input signals

When using the A/D Converter with its sample-and-hold function disabled, make sure the analog input level is fixed

during A/D conversion.

A/D conversion completed bit read timing

To read the A/D conversion completed bit (the Single Mode Register 0 ADSCMP bit or the Scan Mode Register 0

ADCCMP bit), as well as the A/D simultaneous sampling status bit (the A/D0 Single Mode Register 2 ADSH2ST

bit) immediately after A/D conversion has started or has been terminated by the A/D conversion stop bit, be sure

to adjust the timing 6 BCLK periods by performing a dummy read of their registers before read.

Regarding the analog input pins

Appendix Figure 4.10.1 shows the internal equivalent circuit of the A/D Converter’s analog input part. To obtain

accurate A/D conversion results, make sure the internal capacitor C2 of the A/D conversion circuit is charged up

within a predetermined time (sampling time). To meet this sampling time requirement, it is recommended that a

stabilizing capacitor C1 be connected external to the chip.

The method for determining the necessary value of this external stabilizing capacitor with respect to the output

impedance of an analog output device is described below. Also, an explanation is made of the case where the

output impedance of an analog output device is low and the external stabilizing capacitor C1 is unnecessary.

Rated value of the absolute accuracy

The rated value of the absolute accuracy is the actual performance value of the microcomputer alone, with influ-

ences of the power supply wiring and noise on the board not taken into account. When designing the application

system, use caution for the board layout by, for example, separating the analog circuit power supply and ground

(AVCC, AVSS and VREF) from those of the digital circuit and incorporating measures to prevent the analog input

pins from being affected by noise, etc. from other digital signals.

Inside the microcomputer

10-bit A/D Successive

Approximation Register (ADiSAR)

10-bit D/A Converter

Cin : input pin capacitance (approx. 10 pF)

R2 : parasitic resistance of the

selector (1-2 K

C2 : comparator capacitance

(approx. 2.9 pF)

C1 : parasitic capacitance of the board

+ stabilizing capacitance

R1 : resistance of analog output device

Analog output device

E : voltage of analog output device

V2 : voltage across C2

VREF0 : analog reference voltage

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