
11
A/D CONVERTER
11-33
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
11.2.11 10-bit A/D Data Registers
10-bit A/D0 Data Register 0(AD0DT0)
<Address: H’0080 0090>
10-bit A/D0 Data Register 1(AD0DT1)
<Address: H’0080 0092>
10-bit A/D0 Data Register 2(AD0DT2)
<Address: H’0080 0094>
10-bit A/D0 Data Register 3(AD0DT3)
<Address: H’0080 0096>
10-bit A/D0 Data Register 4(AD0DT4)
<Address: H’0080 0098>
10-bit A/D0 Data Register 5(AD0DT5)
<Address: H’0080 009A>
10-bit A/D0 Data Register 6(AD0DT6)
<Address: H’0080 009C>
10-bit A/D0 Data Register 7(AD0DT7)
<Address: H’0080 009E>
10-bit A/D0 Data Register 8(AD0DT8)
<Address: H’0080 00A0>
10-bit A/D0 Data Register 9(AD0DT9)
<Address: H’0080 00A2>
10-bit A/D0 Data Register 10(AD0DT10)
<Address: H’0080 00A4>
10-bit A/D0 Data Register 11(AD0DT11)
<Address: H’0080 00A6>
10-bit A/D0 Data Register 12(AD0DT12)
<Address: H’0080 00A8>
10-bit A/D0 Data Register 13(AD0DT13)
<Address: H’0080 00AA>
10-bit A/D0 Data Register 14(AD0DT14)
<Address: H’0080 00AC>
10-bit A/D0 Data Register 15(AD0DT15)
<Address: H’0080 00AE>
b0
123456789
10
11
12
13
14
b15
ADDT0-ADDT15
000000??????????
<Upon exiting reset: Undefined>
b
Bit Name
Function
R
W
0–5
No function assigned.
0–
6–15
ADDT0-ADDT15
10-bit A/D conversion result
R
–
10-bit A/D data
Note: These registers must always be accessed in halfwords.
During single mode, the 10-bit A/D Data Registers are used to store the result of A/D conversion performed
on each corresponding channel.
During single-shot or continuous scan mode, the content of the A/D Successive Approximation Register is
transferred to the 10-bit A/D Data Register for the corresponding channel when A/D conversion on each
channel has finished. Each 10-bit A/D Data Register retains the last conversion result until they receive the
next conversion result transferred, allowing the content to be read out at any time.
11.2 A/D Converter Related Registers