參數(shù)資料
型號: LSIFC909
英文描述: LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00
中文描述: LSIFC909光纖通道I / O處理器技術(shù)手冊2.1 8 / 00
文件頁數(shù): 85/144頁
文件大?。?/td> 1496K
代理商: LSIFC909
Host Interface Registers
5-29
corresponding mask bit in the
Host Interrupt Mask
register is cleared to 0, a PCI INTA/ interrupt will be
generated.
Register: 0x34
Host Interrupt Mask
Read/Write
The
Host Interrupt Mask
register is used to mask the interrupt conditions
reported in the
Host Interrupt Status
register.
R
Reserved (Read Only)
Reserved for future use.
[31:4]
RIM
Reply Interrupt Mask (Read/Write)
This bit when set to 1 masks the Reply Interrupt condition
(prevents the assertion of PCI INTA/).
3
R
Reserved (Read Only)
Reserved for future use.
[2:1]
DIM
Doorbell Interrupt Mask (Read/Write)
This bit when set to 1 masks the System Doorbell
Interrupt condition (prevents the assertion of PCI INTA/).
0
31
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
4
3
2
1
0
R
RIM
R
DIM
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
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