參數(shù)資料
型號: LSIFC909
英文描述: LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00
中文描述: LSIFC909光纖通道I / O處理器技術(shù)手冊2.1 8 / 00
文件頁數(shù): 16/144頁
文件大?。?/td> 1496K
代理商: LSIFC909
1-4
Introduction
efficiency. Special attention has been given to the design to accelerate
context switching and link utilization.
The LSIFC909 includes a 64-bit, 66 MHz PCI interface to the host
environment. This high speed (528 Mbytes/s), industry standard interface
provides sufficient bandwidth to the host CPU and system memory to
support full duplex FC data rates. The host interface design minimizes
the time spent on the PCI bus for nondata moving activities such as
initialization, command, and error recovery. In addition, the host interface
has the inherent flexibility to support the OEM implementation tradeoffs
between CPU, PCI, and I/O bandwidth.
The high level of integration in the LSIFC909 Controller enables low cost
FC implementations.
Figure 1.1
shows a typical configuration
incorporating the LSIFC909 Controller to implement a FC NL_Port.
Figure 1.1
LSIFC909 Typical Implementation
1.3 Hardware Overview
In today’s fast growing server, RAID, and workstation marketplaces,
higher levels of performance, scalability, and reliability are required to
stay competitive in the SAN market.
2
External
Transceiver
2
LSIFC909
Integrated
Transceiver
Memory
Controller
10
10
2
2
Serial
EEPROM
(2 Kbyte)
Flash
(1 Mbyte)
SSRAM
(1 Mbyte typ.)
Clock
(106 MHz)
32
PCI Bus
32/64
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