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參數(shù)資料
| 型號： | LSIFC909 |
| 英文描述： | LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00 |
| 中文描述： | LSIFC909光纖通道I / O處理器技術手冊2.1 8 / 00 |
| 文件頁數(shù)： | 63/144頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | LSIFC909 |
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Unsupported PCI Commands
5-7
5.4 Unsupported PCI Commands
The LSIFC909 does not respond to reserved commands, special cycle,
or interrupt acknowledge commands as a slave. It never generates these
commands as a master.
5.5 Programming Model
The LSIFC909 host programming model includes all necessary hardware
registers, shared memory and associated memory addresses from the
host (using System Addresses) viewpoint. The host programming model
consists of
PCI Configuration Registers
,
Host Interface Registers
, and a
Shared Memory
region.
5.6 PCI Configuration Registers
The configuration registers are accessible only by the system BIOS
during PCI configuration cycles, and are not available to the user at any
time. No other cycles can access these registers.
Note:
The configuration register descriptions provide general
information only, to indicate which PCI configuration
addresses are supported in the LSIFC909.
Table 5.2
shows
the PCI configuration registers implemented by the
LSIFC909. Addresses 0x48 through 0x7F are not defined.
All PCI-compliant devices, such as the LSIFC909, must support the
Vendor ID
,
Device ID
,
Command
, and
Status
registers. Support of other
PCI-compliant registers is optional. In the LSIFC909, registers that are
not supported are not writable and will return all zeros when read. Only
those registers and bits that are currently supported by the LSIFC909 are
described in this chapter. For more detailed information on PCI registers,
please see the PCI Specification.
PCI configuration space provides identification, configuration,
initialization, and error management functions for PCI devices. The
LSIFC909 provides configuration registers as defined in
Table 5.2
.
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