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參數(shù)資料
| 型號(hào)： | LSIFC909 |
| 英文描述： | LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00 |
| 中文描述： | LSIFC909光纖通道I / O處理器技術(shù)手冊(cè)2.1 8 / 00 |
| 文件頁(yè)數(shù)： | 18/144頁(yè) |
| 文件大?。?/td> | 1496K |
| 代理商： | LSIFC909 |
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1-6
Introduction
1.3.1 PCI Interface
The host PCI interface implements a 64-bit/66 MHz PCI bus. It is
backward compatible with 32-bit and 33 MHz buses. In addition, the PCI
interface provides support for Dual Address Cycle (DAC), PCI power
management, Subsystem Vendor ID and Vendor Product Data (VPD).
Extended access cycles (MRL, MRM, MWI) are also supported.
1.3.2 External 32-Bit Memory Controller
The memory controller provides access to the serial EEPROM, the Flash
ROM, and the 32-bit synchronous SRAM. It supports both interleaved
and noninterleaved configurations up to a maximum of 4 Mbytes of
synchronous SRAM. A general purpose memory expansion bus supports
up to 1 Mbyte of Flash ROM.
1.3.3 Protocol Engine (ARM)
The LSIFC909 uses a 32-bit ARM RISC processor to control all system
interface and message transport functionality. This frees the host CPU
for other processing activity and improves overall I/O performance. The
RISC processor and associated firmware has the ability to manage an
I/O from start to finish without host intervention. The RISC processor also
manages the message passing interface.
1.3.4 System Interface
The system interface efficiently passes messages between the
LSIFC909 and other I/O agents. It consists of four hardware FIFOs for
the message queuing lists: Request Free, Request Post, Reply Free, and
Reply Post. Control logic for the FIFOs is provided within the LSIFC909
system interface with messages stored in external memory.
1.3.5 Link Controller
The integrated Link Controller is FC-AL-2 compatible and performs all
link operations. The controller monitors the link state and strictly adheres
to the loop port state machine ensuring maximum system interoperability.
The link control interfaces to the integrated transceiver and is capable of
supporting the 10b interface specification allowing for an externally
connected 10b (industry standard) FC transceiver.
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