參數(shù)資料
型號(hào): LSIFC909
英文描述: LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00
中文描述: LSIFC909光纖通道I / O處理器技術(shù)手冊(cè)2.1 8 / 00
文件頁(yè)數(shù): 32/144頁(yè)
文件大?。?/td> 1496K
代理商: LSIFC909
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3-2
LSIFC909 Overview
The intelligent LSIFC909 architecture allows the system to specify I/Os
at the command level. The LSIFC909 manages I/Os at the Frame,
Sequence and Exchange level. The LSIFC909 also handles error
detection and I/O retries, allowing the system to offload part of the
exception handling work from the system driver.
3.2 Data Flows
The LSIFC909 uses a 64-bit (33 MHz or 64 MHz) PCI interface or a
32-bit (33 MHz or 64 MHz) PCI interface to pass control and data
information between the system and the protocol controller. This
interface is managed by a Universal PCI Interface (UPI) block, as shown
in
Figure 3.1
. The Data Mover block manages the movement of data
contained in the transmit and receive buffers, from and to the system.
The Data Mover aligns multiple incoming scatter/gather data entries to
the Frame Transmitter. The Frame Transmitter contains separate buffers
for data and control information. The Frame Transmitter uses necessary
context information to create FC frames. Each Data frame contains all or
a portion of a particular scatter/gather entry. The Frame Transmitter also
generates Transmit frames for FC link communication and flow control.
The LSIFC909 Transmit Context Manager block manages the order and
priority of each frame. All frames to be transmitted are passed along to
the Link Controller. Once the Link Controller has been notified of pending
Transmit frames, it begins inserting each frame onto the link. Each byte
within the frame is 8b/10b encoded and transferred to the physical link
using a 10-bit parallel interface or using the serial link with the integrated
transceiver.
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