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參數(shù)資料
| 型號： | LSIFC909 |
| 英文描述： | LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00 |
| 中文描述： | LSIFC909光纖通道I / O處理器技術手冊2.1 8 / 00 |
| 文件頁數(shù)： | 62/144頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | LSIFC909 |
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5-6
Registers
transfer on another bus ownership. The chip issues another Write and
Invalidate command on the next ownership, in accordance with the PCI
specification.
5.3.3.5 PCI Target Disconnect
If the target device issues a disconnect during a Write and Invalidate
transfer, the LSIFC909 relinquishes the bus and immediately tries to
finish the transfer on another bus ownership. The chip does not issue
another Write and Invalidate command on the next ownership unless the
address is aligned.
5.3.4 Read Commands
Memory Read Line and Memory Read Multiple commands are issued
with burst transfers where the memory system and the requesting master
may gain some performance advantage by prefetching read data. Cache
command usage is described below.
5.3.4.1 Memory Read Line
The Memory Read Line command is issued on any burst read of two or
more Dwords in which a cache line boundary is not crossed. The starting
address of the burst need not be aligned to a cache line boundary. This
command allows a capable bridge to prefetch and burst up to an entire
cache line of data, as opposed to disconnecting after every data phase.
5.3.4.2 Memory Read Multiple
The Memory Read Multiple command is issued on any burst read which
crosses a cache line boundary. The starting address of the burst need
not be aligned to a cache line boundary. This command allows a capable
bridge to prefetch multiple cache lines of data, maximizing read burst
potential.
5.3.4.3 Memory Read
For single Dword (nonburst) transfers, the Memory Read command is
used.
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| LSIFC929-329BGA | 制造商:LSI Corporation 功能描述:Fiber Controller 456-Pin BGA |
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