參數(shù)資料
型號(hào): LSIFC909
英文描述: LSIFC909 Fibre Channel I/O Processor technical manual v2.1 8/00
中文描述: LSIFC909光纖通道I / O處理器技術(shù)手冊(cè)2.1 8 / 00
文件頁(yè)數(shù): 33/144頁(yè)
文件大?。?/td> 1496K
代理商: LSIFC909
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Data Flows
3-3
Figure 3.1
LSIFC909 Functional Block Diagram
For incoming serial data, the physical link transfers the data to the Link
Controller using the 10-bit parallel interface or the serial link with the
integrated transceiver. The Link Controller analyzes the received frame
and if appropriate, it passes the frame to the Frame Receiver. The Frame
Receiver strips off the frame header and places it in a separate header
buffer while the data in the frame payload is placed in a data buffer. The
Frame Receiver uses the Receive Context Manager to manage the
received frame’s order and priority. The data contained in the receiver
buffers is associated with a specific scatter/gather entry and passed on
to the Data Mover. The Data Mover aligns the data and passes it on to
the UPI. The UPI requests the PCI bus and bursts the data into system
memory.
The IOP, with its firmware, provides the translation from FC specific
protocols to the high level Block Storage, SCSI and LAN message
interface. This translation integrates the LSIFC909 into the system as if
it were a native parallel SCSI or LAN device, hiding all FC unique
characteristics. Internal communication between the IOP and the Context
Manager occurs over a bus called the Internal Module Bus, which is also
PCI
Bus
TX[9:0]
RX[9:0]
Tx
Context
Managers
(ARM)
Transmit
Buffers
Frame
Transmitter
Data
Mover
Bus
Interface
Unit
UPI-64
32/64
Link
Controller
Frame
Receiver
Receive
Buffers
Integrated
Transceiver
Rx
External Memory
Controller
Protocol Engine
(ARM)
Flash
ROM
Serial
EEPROM
SSRAM
= Data Path
= Control Path
LSIFC909
Internal Module Bus
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